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Posted : adminOn 5/9/2018Syncmate Activation Code Serial Idm. A programmable sequence controller is disclosed utilizing digital and analog inputs in order to generate digital output driver signals for the control of external systems or devices. The controller emulates mechanical sequence drums so that at any one time each of the simulated drums within the controller executes one of the addressable drum lines programmed within the drum. Each line of each simulated drum can be programmed to specify the energization or deenergization of any output driver as well as the energization or de-energization of any memory bit utilized by the controller in order to provide communication between drums. Each drum may also be programmed to have one or two sets of exit conditions, which if met, cause the controller to effectively rotate the drum to a specified drum line and execute this new drum line during the next scan of the controller. The controller can also sense emergency conditions and cause any or all of the drums to rotate to a specified line regardless of the drum line then being executed by the controller for each of the drums.
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An improved power-down, power-up circuitry insures an ordered and complete shutdown of the controller if any of a number of conditions exist, including utility AC failure and impending failure of several of the power supply voltages. Handshaking circuitry between the power supply and the remainder of the controller insures that the controller maintains memory validity for all types of shutdown situations, including momentary losses of any supply voltage. (E) a second logic gate having an input connected to one of the third signals and a second input connected to the fourth signal, the output of the second logic gate connected to an input of said flip-flop for preventing the change of state of said flip-flop after the fourth signal is generated until the third signal is generated, thereby helping to insure that the flip-flop maintains the generation of the fifth and sixth output signals for at least as long as the first time delay generated by the time delay and amplifying circuitry, and. Whereby the programmable sequence controller enters a hold or standby state whenever a power or operating failure is detected by the first logic gate regardless of the duration of the power or operating failure and whereby the controller only resumes normal operation after the power or operating condition has been corrected for said second predetermined length of time as generated by the time delay and amplifying circuit so as to insure that the direct current electrical power means of the controller have entered a quiescent state prior to resumption of controller activity. (E) a second logic gate having an input connected to one of the third signals and a second input connected to the fourth signal, the output of the second logic gate connected to an input of said flip-flop for preventing the change of state of said flip-flop after the fourth signal is generated until the third signal is generated, thereby helping to insure that the flip-flop maintains the generation of the fifth and sixth output signals for at least as long as the first time delay generated by the time delay and amplifying circuitry, and. Whereby the programmable sequence controller enters a hold or standby state whenever a power or operating failure is detected by the first logic gate regardless of the duration of the power or operating failure and whereby the controller only resumes normal operation after the power or operating condition has been connected for said second predetermined length of time as generated by the time delay and amplifying circuit so as to insure that the direct current electrical power means of the controller have entered a quiescent state prior to resumption of controller activity.
